The next stage in AI power? XConn set to reveal end-to-end PCIe Gen 6 offering higher bandwidth than ever
- Apollo 2 switch supports Gen 6.2 and CXL 3.1 inside a single hybrid chip
- XConn wants to redefine bandwidth limits, but real-world results remain completely untested
- Intel and XConn are collaborating to test full-stack compatibility in PCIe-based ecosystems
XConn Technologies is preparing to demonstrate what it describes as a fully integrated, end-to-end PCIe Gen 6.2 and CXL 3.1 solution at the upcoming Future of Memory and Storage (FMS25) event.
The company is positioning the launch as a critical step toward meeting the performance needs of AI and data center workloads.
However, as with any early-stage technology demo, real-world scalability and reliability are still open questions.
Hybrid switch with theoretical flexibility
The company’s Apollo 2 switch will be the core of this unveiling – marketed as the industry’s first hybrid switch to support both PCIe Gen 6.2 and CXL 3.1 within a single chip, it is said to simplify interconnect designs and enhance scalability.
“XConn is excited to bring to market PCIe Gen 6.2 and CXL 3.1 switches, with samples now available,” said Gerry Fan, CEO of XConn Technologies.
“As the industry accelerates toward more memory-centric and performance-intensive architectures, our commitment is to empower customers with best-in-class.”
These benefits are aimed at reducing complexity in data centers while enabling broader architectural flexibility.
Although technically promising, the actual advantage of such integration will depend on performance outcomes under production-grade workloads.
XConn’s collaboration with Intel is also being positioned as a major development, as according to Intel Senior Fellow Ronak Singhal, the partnership will help ensure that both software and hardware components interact smoothly, offering “robust end-to-end solutions.”
The companies expect this effort to foster an interoperable environment for PCIe and CXL technologies.
Still, past experiences in the industry suggest that successful validation often takes time and more than one demo cycle.
The upcoming demo will showcase low-latency, high-bandwidth switching, highlighting the infrastructure’s readiness for applications such as AI/ML model training, cloud computing, and composable infrastructure.
XConn’s booth will reportedly feature a fully standards-based setup, but until benchmarks are released, it is difficult to determine how much improvement users can expect compared to existing PCIe Gen 5 deployments.
XConn has also partnered with ScaleFlux to improve CXL 3.1 interoperability for AI and cloud infrastructure.
While this indicates momentum, it does not confirm how well the solution integrates with the kinds of workloads currently stressing today’s architectures.
The implications for high-speed storage are significant if the technology delivers.
With increasing demand for the largest SSD capacities and the fastest SSD performance, PCIe Gen 6 could support faster data transfers between storage devices and processing units.
Still, these theoretical gains must be tempered with skepticism until field data confirms the impact.
XConn’s demo may well mark the beginning of the next chapter in AI hardware. But for now, it remains a preview, not a proof point.
Via Techpowerup
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Apollo 2 switch supports Gen 6.2 and CXL 3.1 inside a single hybrid chip XConn wants to redefine bandwidth limits, but real-world results remain completely untested Intel and XConn are collaborating to test full-stack compatibility in PCIe-based ecosystems XConn Technologies is preparing to demonstrate what it describes as a fully…
