Take a peek at what AMD’s next generation Venice Zen 6 EPYC CPU CCD looks like as CEO shows its die
- AMD shows off its first 2nm-class Venice CPU die built using TSMC’s N2 node
- Venice, built on Zen 6, targets high-performance computing workloads
- AMD and TSMC hope to deepen their collaboration for future innovations
AMD has announced it has successfully produced the first 2nm-class silicon for its next-generation EPYC processor, codenamed “Venice” which is expected to launch in 2026 as part of AMD’s 6th Generation EPYC lineup.
The core complex die (CCD) is the first high-performance computing product to be taped out and brought up using TSMC’s advanced N2 process technology.
The Venice CPU, built on the Zen 6 architecture, brings AMD one step closer to delivering on its data center roadmap and will target HPC workloads when it launches. With the move to the 2nm node, AMD expects to offer better power efficiency, performance, and silicon yields.
Driving significant technology scaling
“TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing,” said AMD Chair and CEO Dr. Lisa Su.
“Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing,” Dr. Su added.
TSMC CEO Dr. C.C. Wei, who posed alongside Dr. Su with the CCD for the photo above, echoed the sentiment, saying, “We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab. By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing.”
In separate news, AMD also announced that has validated the silicon for its 5th Gen EPYC CPUs at TSMC’s Fab 21 site in Arizona.
This will allow AMD to manufacture some of its current-generation processors in the US, marking a step forward for the company’s domestic production capabilities, something that is being championed by President Donald Trump.
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AMD shows off its first 2nm-class Venice CPU die built using TSMC’s N2 node Venice, built on Zen 6, targets high-performance computing workloads AMD and TSMC hope to deepen their collaboration for future innovations AMD has announced it has successfully produced the first 2nm-class silicon for its next-generation EPYC processor,…
