Nvidia unveils custom high-bandwidth memory promising higher bandwidth and lower power use – but who will actually get to use it?

• September 4, 2026

• Nvidia’s NVHBM moves the memory controller off the accelerator die and into the HBM stack’s base die, allowing it to claim a potential 30% more bandwidth, 15% lower HBM power, and 25% more compute area versus standard HBM4E
• Nvidia’s NVHBM performance comparisons are linked to HBM4E, which is still in the sampling stage, with a launch expected sometime in 2027
• Access to the custom solution is gated behind NVLink Fusion; Amazon’s Annapurna Labs is the only named partner so far and has not said which GPU uses that memory

On August 26, Nvidia extended its NVLink Fusion program with NVHBM, a custom high-bandwidth memory architecture that the company says delivers up to 30% more memory bandwidth per stack, 15% lower HBM power consumption, and up to 25% more usable area on the accelerator die.

The performance was measured against standard HBM4E samples even as the memory is expected to ship in volume some time in 2027.

Amazon‘s Annapurna Labs is the first named partner for Nvidia’s memory advance which aims to address growing performance limitations for frontier-level AI models centering around limited bandwidth.

What makes NVHBM tick?

Nvidia’s approach doesn’t reinvent how memory is handled; it reimagines where it is managed. Conventional HBM approaches split this between two companies: the memory vendor supplies the DRAM stack and its base die, and the accelerator designer puts the memory controller and physical interface on its own compute die.

JEDEC standardizes the connection between the two at the cost of a very wide, comparatively slow parallel bus. NVHBM dissolves the seam altogether by moving Nvidia’s memory controller into the base die of the 3D stack, replacing the standard bus with a narrower, serialized die-to-die link that Nvidia designs and memory makers can build.

Nvidia’s technical blog puts the resulting reduction in interface and support area at up to 67% against the JEDEC HBM4E standard, even as it improves key power consumption, memory bandwidth, and usable area.

The underlying tech is not completely new, however: Marvell announced the same basic idea in December 2024, naming Micron, Samsung, and SK hynix as collaborators while claiming up to 25% more compute area, 33% greater memory capacity, and a 70% reduction in memory interface power, figures that come close to what Nvidia is currently projecting. Counterpoint Research analyst Neil Shah put it plainly: “The technology is not new. The distribution is.”

Even as HBM4E remains elusive, as it is not in mass production just yet, with Samsung shipping the first HBM4E samples in late May 2026 and SK hynix pulling its own sampling forward to around June, NVHBM is even more elusive. It is a building block gated behind NVLink Fusion, Nvidia’s program for connecting third-party accelerators to its rack-scale platform, and access runs through that program’s partner list.

Amazon’s Annapurna Labs is the first named participant, with Nvidia’s blog saying Annapurna will support NVLink Fusion with Trainium4 without explicitly mentioning NVHBM.

For now, NVHBM might be the future, but it may arrive well after HBM4E is already being deployed en masse. Nvidia’s own technical blog describes NVHBM as built on the same technology the company will use for future GPUs, without specifying the first generation that would support it natively.

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Nvidia’s NVHBM moves the memory controller off the accelerator die and into the HBM stack’s base die, allowing it to claim a potential 30% more bandwidth, 15% lower HBM power, and 25% more compute area versus standard HBM4E Nvidia’s NVHBM performance comparisons are linked to HBM4E, which is still in…