A tiny firm wants to slash energy consumption by changing the way CPUs are designed – and it is even planning a new high performance server chip
- NeoLogic raises $10 million to advance CMOS+ CPUs, reducing circuit complexity
- CMOS+ enables 6-32 input gates, reducing power use and die size
- First processors expected in 2026, targeting energy efficient AI data center workloads
NeoLogic has raised $10 million in in Series A funding as it works to change how processors are designed.
Founded in 2021, the Israel-based company (with a US presence planned for the future) is not focusing on transistor scaling, the traditional path of the semiconductor industry, but rather on reducing the complexity of circuits.
Its CMOS+ technology integrates standard CMOS gates with reduced complexity gates, cutting transistor counts by as much as three times at any process node.
Up to 50% lower energy use
Conventional CMOS is limited by fan-in, with gates typically handling no more than four inputs.
Designers rely on tree structures to handle higher inputs, which increases both chip area and power use.
NeoLogic’s CMOS+ enables single stage gates that handle between 6 and 32 inputs, shortening the critical path while reducing area and energy consumption.
The company says processors built with CMOS+ can lower power use by up to 50 percent and reduce chip area by up to 40 percent while keeping latency on par with current designs.
These improvements are compatible with existing CMOS manufacturing processes, from 130nm down to 2nm, as well as standard EDA tools, so adoption won’t require new infrastructure.
By cutting die size and improving yield, CMOS+ provides cost advantages at advanced nodes, where wafer costs and development expenses rise sharply.
It’s more than just gates, however, as CMOS+ also offers power efficient registers, buffers, and arithmetic blocks. Together, NeoLogic says, these elements give chip designers a new infrastructure that simplifies processor design while achieving better power and area tradeoffs.
“We are backing NeoLogic as they push the boundaries of computing with their breakthrough approach to energy-efficient processors,” said Talia Rafaeli, Partner at KOMPAS VC, which led the latest funding round. “The team’s deep technical expertise and innovative CMOS+ technology position them to impact the AI data center space significantly.”
NeoLogic sees CMOS+ as a way to deliver more efficient computing without departing from established tools and processes. It has begun demonstrating its first processors to customers and expects deployment in data centers starting in 2026.
Via eeNews Embedded
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NeoLogic raises $10 million to advance CMOS+ CPUs, reducing circuit complexity CMOS+ enables 6-32 input gates, reducing power use and die size First processors expected in 2026, targeting energy efficient AI data center workloads NeoLogic has raised $10 million in in Series A funding as it works to change how…
